FIG. 5 illustrates the basic layout of a digital PLL circuit that contains an analog loop filter. This PLL circuit comprises a clock signal input/output type phase comparing circuit 100, an analog loop filter 102, and an analog input/output type voltage-controlled oscillator (VCO) 104. An input clock signal INCK and the feedback clock signal PLLCK output from VCO 104 are input to phase comparing circuit 100, which outputs analog phase error signal Φer representing the phase error of the two clock signals INCK, PLLCK. Loop filter 102 is a low-pass filter, which integrates phase error signal Φer output from phase comparing circuit 100. The output voltage of loop filter 102 is a control voltage Sv, which is input to VCO 104. VCO 104 oscillates and outputs variable frequency clock PLLCK whose frequency corresponds to control voltage Sv. When the phase error of input clock INCK and VCO clock PLLCK of the PLL circuit is not zero, the phase error signal Φer passes through the loop filter and is output as control voltage Sv, which is fed to VCO 104, and the frequency of clock PLLCK is changed until the phase error becomes zero.
Typically, loop filters 102 are classified as active types comprising op amps and passive types made up of RC circuits. FIG. 6 illustrates an example layout of an active type filter. The illustrated active loop filter 102 includes an integrator comprising an op amp 106 as well as an input resistor 108 and an RC feedback circuit (110, 112). In this integrator, the output terminal of phase comparing circuit 100 is connected to inverting input terminal (−) of op amp 106 via input resistor 108, reference voltage VREF is applied to non-inverting input terminal (+), and resistor 110 and capacitor 112 are connected in series between inverting input terminal (−) and the output terminal. The transfer function or integration constant of the loop filter 102 is a function of the resistance values of input resistor 108 and feedback resistor 110 and of the capacitance of capacitor 112.
Phase comparing circuit 100 includes a comparator (not shown in the figure) that outputs an up signal UP or down signal DW corresponding to the phase error of the two clock signals INCK and PLLCK, and charge pump circuit 114 in the output section or a subsequent section. If the phase of PLL clock PLLCK leads the phase of input clock INCK, the up signal UP is output from the comparison part. During the period of output of the up signal UP, switch 116 on the positive electrode side power source voltage Vdd side of charge pump circuit 114 is turned on. As a result, phase error signal Φer increases, output voltage Sv of loop filter 102 decreases, and the frequency of PLL clock PLLCK moves lower. When the phase of PLL clock PLLCK lags the phase of input clock INCK, down signal DW is output from the comparison part, and during the period when down signal DW is output, switch 118 on the negative electrode side power (source voltage Vss side) of charge pump circuit 114 is turned on. As a result, phase error signal Φer decreases, output voltage Sv of loop filter 102 increases, and the frequency of PLL clock PLLCK moves higher.
Reference voltage VREF applied to the non-inverting input terminal (+) of op amp 106 may be set at any voltage value. When charge pump circuit 114 is set in the output section of phase comparing circuit 100 as described above, it may also be set at the central level of the power source voltage (Vdd/2). Also, one may also adopt the following method: In charge pump circuit 114, a constant-current source (not shown in the figure) for the source current may be set between the positive electrode side power source voltage terminal and switch 116, and at the same time, a constant current source for the sink current (not shown in the figure) may be arranged between switch 118 and the negative electrode side power source voltage terminal. Switches 116, 118 are usually made up of transistors.
In this way, as loop filter 102 is an active filter, compared with the passive type, not only can a higher gain be obtained, but it is also possible to prevent the variation in the output of loop filter 102 (that is, control voltage Sv) from influencing the input to loop filter 102 (that is, the output of phase comparing circuit 100), which is advantageous. In particular, for PLL circuits used in clock data recovery (CDR) in the reproduction of optical disks, the as CDs (Compact Disks), DVDs (Digital Versatile Disks), etc., because the control voltage varies as a function of the reproduction speed, an active type filter is preferred. With the passive type filter, the variation in the control voltage is transmitted via the loop filter to the output of the phase comparing circuit, and has an adverse influence on the balance of the source current/sink current in the charge pump circuit, so that the lock point of the signal reproduction tends to deviate. With the active type filter, even when the control voltage varies according to the reproduction speed, because the variation in the voltage is not transmitted to the output of the phase comparing circuit, the balance of the source current/sink current in the charge pump circuit does not collapse, and it is possible to hold the lock point of the signal reproduction over a wide band with high stability.
However, because the active type loop filter makes use of the op amp, the offset of the attached parts to the op amp has an adverse influence on the various characteristics of the PLL circuit, which is undesirable. For example, in a PLL circuit for optical disk reproduction, the input signal is not the clock itself. Instead, the input signal is given as a binary pulse sequence signal or serial data stream having plural types of pulse widths. For the PLL circuit, it is necessary to have a function in detecting the regularity of the serial data stream and to read the channel clock information from each pulse edge (extraction). For this purpose, in addition to expanding the locked range, a frequency comparing circuit is set in phase comparing circuit 100 or parallel to it. The frequency comparing circuit can form a frequency-locked loop with loop filter 102 and VCO 104.
For this type of application, the problem is that the serial data stream may be cut off instantly in reproduction due to fingerprints, dirt, scratches, etc. on the surface of the optical disk. In the case, from the former-section circuit or control circuit that detects that the reproduction RF signal is missing, defect signal DF is generated, and, corresponding to this defect signal DF, the VCO oscillation frequency is held. For example, in the configuration shown in FIG. 6, when defect signal DF becomes active (on), two switches 116, 118 of charge pump circuit 114, are forcibly turned on at the same time. As a result, the output of charge pump circuit 114 becomes a high impedance as viewed from the side of input resistor 108. At this time, the path from the output of charge pump circuit 114 to input resistor 108 has an impedance very high (ideally, infinitely high) so that the resistance of input resistor 108 with respect to the inverted input (−) of op amp 106 can be ignored. Consequently, the integration speed becomes infinitely slower, and, it seems that the output voltage of op amp 106, that is, VCO control voltage Sv, is held in this state. As a result, VCO 104 can go into self-running mode while the oscillation frequency right before cut off of the serial data stream is maintained as is.
However, when op amp 106 has an offset, the offset voltage becomes DC related to the hold state, and, although defect signal DF goes on, VCO control voltage Sv varies, so that undesired changes take place in the oscillation frequency of VCO 104. If the changes in the oscillation frequency are within the lock range (phase pull-in range) of phase comparing circuit 100, there are no problems. However, if they go out of the lock range, frequency-locking deviates. As a result, it is necessary to start the frequency-locked loop after the release of defect signal DF so as to pull in the frequency to start over again, and it takes a long time to re-establish phase locking. As the time for re-establishing the phase locking becomes longer, during reproduction of CD or DVD playback, data may be skipped, causing audio gaps or freezing of the picture, which is undesirable for the user in enjoying the program.
Another disadvantage when there is an offset in the op amp of the active type loop filter is in the reduction in the phase margin during locking of the pulse sequence of the serial data stream with the PLL clock signal. Usually, the serial data stream read from the optical disk or the like has a significant jitter component due to variation in the bit length when the disk is manufactured. Consequently, like judgment of a 0 or 1 at the center of the eye pattern, if locking is not realized for the center of the eye pattern, it is quite possible that erroneous data detection will take place under influence of the jitter. Consequently, in the PLL circuit for CDR, timing design is performed so that with PLL clock locked to the channel clock, the edge of the PLL clock (lock point) comes to the center of the eye pattern. However, when there is an offset in the loop filter, the lock point deviates from the center of the eye pattern corresponding to the magnitude of the offset. As a result, the error rate of the reproduction data increases.
In the prior art, although there exists certain offset in the op amp of the loop filter, the influence of offset can be avoided by adjusting the values of input resistor 108 and feedback circuit (110, 112) so as to lower the speed of the integrator (the gradient of the output variation slope). However, there has been a trend to increase of the frequency of the serial data stream for higher speed, and, as a result, in the reproduction of optical disk, there is a demand for higher speed for the pull-in characteristics from the seek operation in the reproduction of the optical disk. Consequently, it is necessary to increase the speed of the integrator in the loop filter, and it is necessary to sacrifice the offset resistance of the op amp. In this way, for the method of adjustment of the characteristics of the integrator in the loop filter, there is a trade-off between the various required properties, so that it is impossible to improve all of the required properties at the same time.
The purpose of the present invention is to solve the aforementioned problems of the prior art by providing a phase-locked loop (PLL) circuit characterized by the fact that it can automatically correct for the offset of the analog (especially the active type) loop filter and it can improve the stability and precision for the locked clock and frequency.